Difference between Wire and Logic data types in System Verilog.

WIRE:

1) If "wire" left unconnected then it shall have value 'Z.

2) "wire" acts as a physical connection between different elements and it doesn't store any values.
   For example, wire a = b; statement connects "b" element to "a" element.

3) "wire" can be used in module ports and in fact module ports default type is "wire".

4) If multiple drivers are driving to a "wire" element through continuous assignment("assign" statement) than the result would be 'X. Therefore multiple drivers/race condition produce undefined output value on "wire" type element.

Following is the example that shows race condition in case of multiple drivers are driving different value to a "wire" element.

module top();
  bit[1:0] drv1=1, drv2=2;

  wire[1:0] wire_type;

  // MULTIPLE DRIVERS 

  assign wire_type = drv1;

  assign wire_type = drv2;

   

  initial begin

    repeat(4) begin

      $display("Value of wire_type = %0h at time = %0tns", wire_type, $time);

      #5ns;

    end

    $stop();

  end

endmodule

RESULT:

Value of wire_type = X at time = 0ns

Value of wire_type = X at time = 5ns

Value of wire_type = X at time = 10ns
Value of wire_type = X at time = 15ns

5) "wire" cannot be driven in a procedural block. An example is stated below with the simulation result.

module top();
  bit clk;
  bit[1:0] drv1=1, drv2=2;
  wire[1:0] wire_type;

  always #5ns clk = ~clk;

  //MULTIPLE DRIVERS

  always @(posedge clk) wire_type =drv2;

  always @(posedge clk) wire_type =drv1;

  initial begin

    repeat(4) begin

      $display("Value of wire_type = %0h at time = %0tns", wire_type, $time);

      #5ns;

    end

    $stop();

  end

endmodule

RESULT:

Error-[IBLHS-NT] Illegal behavioral left hand side

testbench.sv, 16

  Net type cannot be used on the left side of this assignment.

  The offending expression is : wire_type

  Source info: wire_type = drv2;

Error-[IBLHS-NT] Illegal behavioral left hand side

testbench.sv, 17

  Net type cannot be used on the left side of this assignment.

  The offending expression is : wire_type

  Source info: wire_type = drv1;

LOGIC:

1) If "logic" left unconnected then it shall have the value 'X.

2)  "logic" can be driven by a continuous assignment ("assign" statement), in module ports or inside a procedural block.

3) Multiple drivers to the "logic" element in continuous assignments do not allow. 

For example: 

  assign logic_type = drv1;

  assign logic_type = drv2;

In above case, simulator shout errors for multiple drivers.

4) In case multiple drivers are driving different values to a "logic" element in procedural blocks then the "logic" element simply assigns the value from the last assignment.

Below is the example with the simulation result.

module top();

  bit clk;

  bit[1:0] drv1=1, drv2=2;

  logic[1:0] logic_type;

  always #5ns clk = ~clk;

  

  //MULTIPLE DRIVERS

  always @(posedge clk) logic_type = drv2;

  always @(posedge clk) logic_type = drv1;

  initial begin

    repeat(4) begin

      $display("Value of logic_type = %0h at time = %0tns", logic_type, $time);

      #5ns;

    end

    $stop();

  end

endmodule

RESULT:

Value of logic_type = X at time = 0ns

Value of logic_type = X at time = 5ns

Value of logic_type = 1 at time = 10ns

Value of logic_type = 1 at time = 15ns

I hope the above points related to "wire" and "logic" will help to understand the difference between both of them. If you any comment or feedback, please in the comment box.